1. Field of the Invention
The present invention relates to a flash memory cell structure, and more particularly to a charge trap memory cell structure with multi-doped layers at the active region, to a fabricating method and an operating method thereof, and to a flash memory array using the charge trap memory cell and an operating method of the same.
2. Description of Related Art
Flash memory is a class of non-volatile semiconductor memories which can erase data by a block unit over several tens and hundreds of bytes, and record data by a byte or page unit, and it is distinguished from EEPROM which can erase and record data by a cell unit.
The importance of a non-volatile semiconductor memory has been increasing due to a gaining popularity of modern mobile and multimedia computing environments such as mobile phones, PDAs, MP3 players, USB drives, and so on, and to an increasing necessity for a portable recording device suitable for large amount of information. Therefore, a reduction in cell size and electric power consumption and a high speed operation have been needed to meet an increase in consumption for a flash memory.
A conventional flash memory is classified as NOR and NAND type, according to its array organization of unit cells. In a NOR type flash memory, cells are connected in parallel, and in a NAND type, cells are connected in series between a bit line and a source line. NOR type is mainly used for code storage, where the program or the operating system is stored and executed by the microprocessor or microcontroller. NAND type is for data storage, where data files for image, music, and voice are recorded and read sequentially.
To attain a large capacity, low power-consumption, and rapid flash memory, there has been necessarily a need for developing the essential memory cell.
However, as the device dimensions enter into the ultimate scaling limit of the nanometer regime, cell reduction is facing challenging issues in the FLOTOX (Floating-Gate-Tunneling-Oxide) cell, as shown in FIG. 1. This is because a decrease in a gap between cells causes coupling of floating gates and increases a mutual interferences between cells. Referring to FIG. 1, reference number 41 indicates an oxide layer, 43 means a nitride layer, 47 means a tunnel oxide layer, 50 means a gate, 52 is a floating gate, 30 is a source or drain, and 10 indicates a semiconductor substrate.
Accordingly, in recent times the charge trap flash memory device, wherein the structure has a simple process for fabricating and little dependence on a coupling, and in the MOSFET structure as shown in FIG. 2, multi-dielectric layers (40) have been inserted in place of a gate oxide layer, and they function as a charge trap layer, has gained its popularity as the flash memory cell of the next generation. There are typical examples of the charge trap flash memory cell such as SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon), and MNOS (Metal-Nitride-Oxide-Silicon), and these all utilize lots of deep level traps which exist inside the nitride layer (44) of the multi-dielectric layers (40). Referring to FIG. 2, reference number 42 indicates a blocking oxide layer, 46 means a tunnel oxide layer.
However, the conventional charge trap memory cells have been generally manufactured in the NMOS type as well as the floating gate memory cells (FLOTOX cells). For that reason, Channel-Hot-Electron (CHE) injection or Fowler-Nordheim (F-N) tunneling injection has been used to inject electrons into the nitride layer of the multi-dielectric layers for programming.
With the CHE injection scheme, injected electrons hardly move laterally within the nitride layer due to the separated nitride traps, but they are distributed almost around the upper part of the drain or source, where electrons were injected, and such a feature makes it possible to store two bits in a single cell. The CHE injection scheme has been used successfully in Virtual Ground Array, named of NROM™ or MirrorBit™, which is classified as a NOR flash memory.
But there were some problems in the CHE injection scheme. Because the CHE injection scheme needs a large lateral electric field on a channel for programming, it should be able to apply different voltages freely to both the source and drain respectively (IEEE Elec. Dev. Lett., vol. 21, pp. 543-545, 2000). And there are limitations on downscaling the channel, due to interference between trapped electrons, a transfer of electrons to neighboring trap regions, and so on. Also, there is another drawback in that inefficiency of injection makes the electric power consumption high (Trans. Electron Dev., vol. 49, no. 11, pp. 1939-1946, 2002).
The conventional charge trap memory cell has advantages in that there is no need for a floating gate and the simple structure, which can be accomplished only by the multi-dielectric layers, makes the manufacturing process easier. But it has a decisive drawback in that it is very difficult for the charge trap memory cell to remove electrons injected by programming.
The deep level traps in the nitride layer prevent once-injected electrons from leaving, and it improves electron retention. But it causes a huge rise in operating voltage for erasing.
It is generally explained that when a high negative bias is applied to a gate, electrons cannot be easily ejected from a deep trap in the nitride layer, therefore holes are injected through F-N tunneling from the channel and combined again with already-programmed electrons, and finally the erase operation is accomplished.
However, hole tunneling current is much smaller than electron tunneling current for the same conditions. Comparing with the FLOTOX cell, which uses a floating gate, a conductor, the charge trap memory cell, which uses a dielectric material for electric charge storage, has a very small coupling ratio, and there is a basic limit to concentrate the applied gate voltage on the tunneling oxide layer. Therefore these two factors of low hole tunneling current and a small coupling ratio at severe negative gate voltage cause the back tunnel effect in that electron tunneling starts from the gate, as shown in FIG. 3, and this effect slows down erase speed and stops recovery to the original state of threshold voltage at certain level.
After all, to commercialize the charge trap memory, this drawback of the incomplete erase problem should be overcome.
At present, NROM™ charge trap memory, which stores two bits per cell, uses the hot hole injection scheme to solve the erase problem. In this scheme, as shown in FIG. 4, when a high negative voltage that is reverse biased is applied between the source or drain and body in the NMOS structure, the N+ region of the source or drain under the gate becomes inverted on the surface, and a hole is induced.
Then, a large electric field is built up at the partially induced N+-P+ junction region, resulting in a Band-to-Band Tunneling phenomenon. After that, holes escaping toward the channel are accelerated due to the applied voltage between source or drain and body, and among these, hot holes, which have enough momentum, can be easily injected into the nitride layer with the help of the gate voltage. Such hot holes have much larger energy in comparison with F-N tunneling holes, and they can be effectively injected into the nitride layer in spite of the heavy mass of a hole and a high tunneling barrier.
However, to generate the erase operation by this hot hole injection scheme, there is need to bias a certain voltage to the source and drain as well as to the gate and body, but it is impossible to apply to the NAND type array. With the conventional NMOS type memory cell, applying a negative high voltage to the gate to erase by the hot hole injection scheme causes the channel to turn off due to an accumulation mode, and the voltage provided by the bit line of a conventional NAND array cannot be delivered effectively to the source and drain of each cell, which is connected in series.
Therefore, the delay of charge trap memory commercialization is caused mainly by the erase speed problem of NAND type flash memory by the back tunnel effect because only the F-N tunneling scheme must be used for both program and erase in NAND type flash memory at this time.
On the other hand, there have been various trials to improve the erase speed not by the hot hole injection scheme but by the F-N tunneling scheme.
Among them, Reisinger et al., used a polysilicon doped with P+ rather than N+ on the gate of the charge trap memory cell, and this raised the tunneling barrier between the gate and the nitride layer to lessen the back tunnel effect (Dig. Symp. VLSI Tech., 1997, pp. 113-114). But when a severe negative voltage is applied to the gate word line, valence band electrons at the gate tunnel to the nitride layer and there are still some limits for improving the erase speed.
Other ways to improve the erase speed is to replace the blocking oxide in FIG. 2 with high-k dielectrics (for instance, Al2O3) to increase the capacitance of the blocking layer and concentrate the electric field on the tunnel oxide layer (Ext. Abst. Int'l Conf. Solid State Dev. Materials, 2002, pp. 162-163), or to use metal TaN (TANOS structure), instead of polysilicon for the gate of a charge trap memory cell, heighten the tunneling barrier of a gate, and restrain back tunneling (Tech. Dig. Int'l Electron Dev. Meet., 2003, pp. 613-616). But these ways still have problems in that the use of a high-k material or a metal gate severely diminishes the silicon CMOS technology compatibility, and the difficulty in applying a tunnel oxide layer with more than a specific thickness in the TANOS structure makes the disadvantage of charge retention characteristics insurmountable.